1. Field of the Invention
Aspects of the present invention relate to the formation of integrated circuit devices that incorporate both an array of memory cells and an array of logic circuits on a single chip or substrate in a process flow sharing processing steps in common between the formation of the memory array and the logic array. Other aspects of the invention relate to an integrated circuit incorporating embedded memory dedicated to logic circuits formed on the chip with the memory.
2. Description of the Related Art
For some data processing applications, it has become desirable to provide integrated circuit devices that incorporate on the same chip both arrays of memory cells and arrays of high speed logic circuits like those typically used in microprocessors or digital signal processors. It might, for example, be desirable to provide an array of dynamic random access memory cells within the integrated circuit device to provide dedicated, comparatively high speed access to a significant amount of data storage for the logic circuits of the integrated circuit device. Applications that could benefit from the provision of such embedded DRAM include logic circuits that process large amounts of data, such as graphics processors. Use of embedded memory might also reduce the number of pins or input/output terminals required by the integrated circuit device. Providing both high speed logic circuits and embedded DRAM on the same chip requires that certain aspects of the process flow used for making the chip be dedicated to the formation of logic circuits and that other aspects be dedicated to the formation of memory cells. FIGS. 1-4 illustrate a portion of a process flow that might be used to provide embedded DRAM on an integrated circuit device that includes high speed logic circuits.
FIG. 1 illustrates at an intermediate processing stage an integrated circuit device that will include embedded DRAM and an array of logic circuits. On the left side of the illustrated device is an exemplary DRAM cell and on the right side of the illustrated device is an exemplary logic FET that makes up part of a logic circuit. Other circuitry for performing input/output (I/O) functions for the integrated circuit device would typically be included, but is not shown here. The embedded DRAM cell, when complete, will include a transfer or pass field effect transistor (FET) coupled to a charge storage capacitor. The transfer FET acts as a switch for selectively coupling the lower electrode of the charge storage capacitor to a bit line so that charges, representative of data, can either be read from or stored to the charge storage capacitor. The embedded DRAM and logic circuits of the integrated circuit device are formed on a single silicon substrate 10, which typically has at least a surface layer of P-type material. Device isolation regions 12 are provided as necessary across the surface of the device. The illustrated device isolation regions 12 may be field oxide regions formed in a modified local oxidation of silicon (LOCOS) process or may be shallow trench isolation (STI) devices consisting of trenches filled with oxide by chemical vapor deposition (CVD). The illustrated cross section of the embedded DRAM cell includes a section through a transfer FET 14 and through an adjacent wiring line structure 16. The wiring line structure 16 is typically an extension of the gate electrode structures for adjacent DRAM cells and so has an almost identical structure to the illustrated gate electrode structure. The gate electrode structure includes a gate electrode 20 including at least a lower layer of doped polysilicon provided on gate oxide layer 18. Most typically, the wiring line conductor 22 also includes at least a lower layer of doped polysilicon formed on the field oxide isolation region 12. A capping oxide layer 24 is provided early in processing to protect the gate electrode 20 and wiring line conductor 22. Oxide spacer structures 26 are provided on either side of the gate electrode and wiring lines, typically by CVD silicon oxide deposition followed by an etch back process. Oxide spacer structures 26 provide lateral protection to the gate electrode and wiring line during processing and might also be used in the formation of lightly doped drain (LDD) structures for the source and drain regions of the transfer FETs. Source/drain regions 28 are formed by self-aligned ion implantation of N-type dopants on either side of the gate electrode 20 to complete the transfer FET 14.
Portions of the logic circuitry, schematically illustrated on the right of FIGS. 1-4, are formed nearly contemporaneously with the formation of the transfer FETs of the DRAM array. Depending on design choices, some processing steps may be shared between the embedded DRAM and logic formation processes or wholly distinct processes might be used for forming the DRAM and logic circuits. The exemplary FET 30 of the logic circuit is formed on a gate oxide layer 32 and includes a polysilicon gate electrode 34. It is generally preferred to not provide a silicide layer over the polysilicon gate electrode layer 34 at the illustrated stage of the manufacturing process. Instead, self-aligned silicide ("salicide") process is used to complete the FETs of the logic circuit at a later stage in the manufacturing process. Oxide spacers 38 are formed on either side of the gate electrode 34 and are typically used in defining an LDD structure for the source/drain regions 40 of the logic FETs.
After formation of the FETs for the DRAM array and the logic array, it is typical to provide a thick oxide layer 42 over the entire substrate 10. The oxide layer is deposited to a sufficient thickness to both cover the various device structures and to provide a sufficient thickness for the planarization of the oxide layer 42. Planarization of the oxide layer 42 is important to improve the process latitude for the photolithography and etching steps used to form the lower electrode of the charge storage capacitor. After provision of the planarized oxide layer, a via 44 is formed through the planarized oxide layer to expose the source/drain region 28 to which the charge storage capacitor of the illustrated DRAM cell will be connected. Doped polysilicon is provided within via 44 to form a vertical interconnect 46 between the source/drain region 28 and the lower electrode 48 of the charge storage capacitor. The lower electrode 48 of the charge storage capacitor is typically formed from several layers of doped polysilicon. For the design rules typically used in modem processes, it is important to provide a three dimensional crown or fin capacitor structure for the lower electrode 48 so that it has sufficient surface area to provide a sufficient level of charge storage for the capacitor. Such a crown or fin structure is necessary to ensure that the charge storage capacitor of the DRAM cell stores a sufficiently large charge to facilitate data reading and writing operations as well as to ensure that the stored charge remains on the charge storage capacitor for an acceptable amount of time without requiring a refresh operation. Formation of the charge storage capacitor continues by providing a capacitor dielectric 50 consisting of the three layer oxide/nitride/oxide structure known as ONO over the lower capacitor electrode 48. An upper electrode 52 is formed by providing another layer of doped polysilicon which is patterned in a manner conventional to DRAM arrays. The completed charge storage capacitor is shown in FIG. 2.
After completion of the charge storage capacitor, a mask such as photoresist mask 54 is provided over the FIG. 2 device to cover the embedded DRAM array and to expose the oxide layer 42 over the array of logic circuitry. Etching is performed to remove the thick oxide layer 42 from above the logic circuitry, resulting in the structure shown in FIG. 3. Processing continues on the logic FET 30 to form a silicide layer 66 over the gate electrode 34 and silicide layers 68 over the source/drain regions 40, as shown in FIG. 4. The silicide layers 66, 68 reduce the resistivity and contact resistance of the gate electrode and the source/drain regions. Typically, the silicide layers are formed in a self-aligned silicide ("salicide") process in which a layer of a refractory metal such as titanium is deposited over the exposed polysilicon gate electrode and the exposed silicon source/drain regions. An initial anneal is performed to convert a portion of the deposited metal layer to a metal silicide. An etch is performed to remove unreacted metal and then a second anneal is performed to achieve a low resistivity for the metal silicide layers 66, 68 on the gate electrode 34 and source/drain regions 40. Processing continues to provide a typically multi-layer interconnect structure dedicated to the logic circuitry (not shown). Further processing completes the integrated circuit device which includes both logic circuitry and embedded DRAM circuitry.
To date, providing embedded DRAM for the logic circuits of an integrated circuit device to enhance the performance of the logic circuits and the device as a whole has been an expensive process which exhibits undesirably low yields for the desired integrated circuit device. It is accordingly desirable to provide a better process for forming embedded DRAM integrated circuit devices.